Semiconductor monolithic memory circuits continue to increase in capacity while at the same time, decreasing in size. Due to the large number of cells in memory devices, and the process sophistication required to produce them, it is not uncommon for memory devices to be fabricated with defective cells. Improved fabrication technology and process control can decrease the number of defects appearing in devices, but are rarely successful at completely eliminating such defects.
A second way to eliminate defective memory cells is to design memory devices with spare memory cells, and built-in redundancy schemes to replace defective cells with spare operational cells. It is well known in the prior art to provide one or more redundant rows and columns to a memory cell array. Using a redirectable decoding scheme addresses of defective cells are deselected, and substituted with redundant rows and/or columns.
While the addition of redundant rows and columns provides for the replacement of a limited number of cells and/or rows and columns, multiple column failures, or cell block failures cannot be corrected with just a few redundant rows or columns. To meet the need for these types of failures, improvements in redundancy schemes have included incorporating higher levels, or hierarchies, of redundancy.
Commonly-owned, U.S. Pat. No. 5,337,146, entitled HIERARCHICAL REDUNDANCY SCHEME FOR HIGH DENSITY MONOLITHIC MEMORIES and filed on Jul. 23, 1993, discloses a semiconductor memory device having main memory quadrants with redundant rows and columns, and at least one redundant quadrant having its own redundant rows and columns. The redundant hierarchy allows for the replacement of defective main memory cells with redundant rows, redundant columns, or if necessary, redundant quadrants.
While the use of entire redundant quadrants provides for an improved redundancy scheme, it is at the cost of area on the layout of the integrated circuit. In certain cases, the advantage of providing a redundant array is not worth the cost in area. It is therefore desirable to provide a redundancy scheme that allows for a redundant memory quadrant that does not require an integral block of area equal to a main memory quadrant.
Redundant quadrant schemes, and even local redundant rows have other drawbacks. Redundant memory cells within a redundant quadrant, row or column, may actually require a longer time to access than those within the main memory quadrants. This delay can arise in the case where a significant amount of time is required for the redundancy decoding scheme as it redirects an address from a known "bad" cell in the main memory quadrant to a "good" cell in the redundant quadrant. It is therefore also desirable to provide a redundancy scheme that provides redundant quadrants with memory cell access times that are equal to or shorter than those of the main memory cells.